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NCP1500
PWM Section
The PWM section consists of a PWM comparator, set
dominant latch, slope compensation circuit, current sense
circuit, and current limit circuit.
The NCP1500 operates as a current mode regulator in
PWM mode. In this mode, a PWM pulse from the
synchronization section initiates the output switch
conduction. Output switch conduction is terminated when the
peak inductor current reaches a threshold level established by
the error amplifier. The output switch conduction duty cycle
is allowed to go to 100% to increase transient load response
when going from light load to heavy load.
A reset dominant latch is provided in the NCP1500. A 3
input OR gate controls the reset pin. Any one of the 3 inputs
will terminate output switch conduction. Once terminated,
output switch conduction cannot begin again until the next
PWM pulse. The only state the NCP1500 does not switch
every cycle is if the 5% overvoltage comparator trips. When
the comparator trips, the switching regulator will remain off
until the voltage drops below the nominal voltage. This state
is similar to a PFM mode of operation. Output switch
conduction can begin at the next PWM cycle after the OVP
input is reset.
Current mode controllers can exhibit an instability at duty
cycles over 50%. A slope compensation circuit is provided
inside the NCP1500 to overcome the potential instability.
Slope compensation consists of a ramp signal generated by
the synchronization block and adding this to the current
signal. The summed signal is then applied to the PWM
comparator.
A current limit feature is provided in the PWM mode only.
The current limit is set to allow peak switch current in excess
of 800 mA. It is implemented as a cycle ? by ? cycle current
limit. Each on ? cycle is treated as a separate situation.
Current limiting is implemented by monitoring the output
switch transistor current buildup during conduction. An
error signal is generated upon sensing an over ? current
condition. This signal is subtracted from the error amplifier
output. This in turn reduces the PWM comparison threshold
voltage, thus limiting the output duty cycle.
3.6040
3.6000
3.5960
400 m
200 m
0.00
400 m
300 m
200 m
400 m
100 m
? 200 m
1.01
1.00
990 m
3.70
1.35
V IN
I FET
I L
I diode
V O
V LX
? 1.00
198.0
201.0
204.0
207.0
210.0
213.0
TIME ( m )
Figure 4. PWM Waveforms During Normal Operation
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